This application is related to U.S. Patent application entitled, xe2x80x9cUsing a Timing Strobe for Synchronization and Validation in a Digital Logic Devicexe2x80x9d of Borkar et al., filed on the same date as this application and assigned to the same assignee.
This invention is related to the high speed transmission of digital data from one chip or integrated circuit package to a number of such devices together with and in sync with a digital timing strobe.
A common way to transmit data, such as digital content, addresses, and/or control bits, from one device to several others in an electronic system is to connect each device to a parallel bus. Each device can transmit or receive data by accessing the same signals on the set of wires of the parallel bus, at different locations along the bus. In contrast, with a point to point bus, the data is relayed from one device to the next over different segments of the bus. At very high transmission rates, such as several hundred megabits per second and higher, precise timing is needed at each device to read or write each bit of data in a bit stream.
One way to provide precise timing on the parallel bus is to transmit a digital clock signal that is synchronized with the transmission of the first bit. This clock signal helps define each interval in which a bit is to be read by a receiving device on the bus. Such a technique, however, is not accurate at high transmission rates because the edges of the clock, as it is received by devices on the bus that are physically far away from the source device, have been skewed or exhibit jitter. In other words, the clock timing seen at the source is significantly different than the clock timing seen at the distant device. Since the bit stream and the clock may not be subject to jitter in the same amount by the time they reach the distant device, there is a serious risk that distant devices will fail to properly detect the bit stream, thereby limiting the high speed performance of the system.